1. Field of the Invention
This invention relates to syllabic filters suitable for use in controlling the step size in a continuously variable slope delta (CVSD) CODEC.
2. Description of the Prior Art
Analog-to-digital converters convert an analog signal, typically an analog voltage, into a digital signal. This necessarily requires quantizing the range of analog signal into a number of discrete voltage ranges. For example, in one system a binary system of 000 will be generated for all voltages ranging from 0 to 0.1 volts, a binary 001 signal will be generated for all voltages greater than 0.1 volt and not greater than 0.2 volts, etc.
In some applications, this technique of utilizing voltage steps of a fixed size over the entire range of input voltages is adequate. However, in many instances, in particular in the digital-to-analog and analog-to-digital conversion of speech signals, for example in the operation of a coder-decoder (CODEC), the use of a large step size will effectively preclude accurate conversion of low level signals, thereby providing unacceptable distortion of the signal. On the other hand, the use of a fixed step of small value, while preventing distortion of low level signals, results in a large number of discrete steps over the entire range of input signals, thereby requiring the digital word representing the analog signal to be rather large. The larger the word size, the greater the transmission rate required to transmit the digital representation of an analog signal.
In order to minimize the transmission rate and yet provide a high quality output signal with little distortion, compressor/expanders (companders) are used. It has been found that rather large step sizes may be used when converting speech signals lying in the middle and high end of the speech signal amplitude range without causing excessive distortion of the speech signal. Accordingly, it is highly desirable to utilize a digital-to-analog or analog-to-digital conversion technique which does not use a plurality of steps of equal size, but which uses small steps for the conversion of low level signals, and larger steps for the conversion of larger signals. One technique for doing this is called the continuously variable slope delta (CVSD) modulator, which provides a plurality of steps, each step being of a different size. The smallest step is used to convert low level signals (i.e., those signals having amplitudes near 0 volts), and the steps increase in size, with the largest step being used to convert the largest signals (i.e., those signals having amplitudes of .+-.Vref, where Vref is the magnitude of the reference voltage used in the CVSD modulator). This nonlinear digital to analog conversion effectively compresses the input analog signal amplitude range from 0 to .+-.Vref, as shown in FIG. 1. This compressed, digital signal is then transmitted to an expander, which converts the compressed digital signal to an expanded analog signal which is a good reproduction of the input analog signal.
One prior art circuit for generating the required step sizes used in a CVSD CODEC is shown in the block diagram of FIG. 2. The analog input signal Vin to be converted is applied to the noninverting input lead 11 of comparator 12. The output signal from comparator 12 is applied via lead 13 to coincidence logic 14. Coincidence logic 14 serves to detect when the output signal from comparator 12 has been continuously either high or low for a plurality of samples, thus indicating that the output signal generated by encoder filter 17 (which is fully described later) is not accurately following the input signal. The output signal from coincidence logic 14 is applied to syllabic filter 15. Syllabic filter 15 establishes the integrating voltage ("step size") used by encoder filter 17 used by the CODEC at any particular time during the analog-to-digital or digital-to-analog conversion process. Thus, if the output signal from encoder filter 17 does not "track" the input voltage fast enough, sylabbic filter 15 increases the step size. The output signals from comparator 12 and syllabic filter 15 are applied to polarity switch 16. Polarity switch 16 serves to provide either a positive or a negative voltage to encoder filter 17, depending on whether encoder filter must increase or decrease its output voltage in order to match the input signal Vin. The output signal from polarity switch 16 is applied to encoder filter 17, which serves to integrate the signals received from polarity switch 16 to provide an output signal which matches the input signal Vin. In turn, the output signal from encoder filter 17 is applied to the inverting input lead 18 of comparator 12. The delta modulated digital output signal representing the analog input signal applied to input terminal 11 is provided by the output signal bit stream from comparator 12 made available to other circuitry (not shown) on output terminal 21.
The companding action provided by the circuit of FIG. 2 improves the signal to noise performance of the CODEC, as compared with CODECs which utilize a fixed step size which is too great to accurately reproduce low level input signals Vin. The companding action provided by the circuit of FIG. 2 also decreases the bit rate which is required by delta modulators which utilize a fixed step size which is sufficiently small to allow proper reproduction of low level input signals Vin, but which is much smaller than the step size required to accurately reproduce large level input signals Vin.
One type of prior art syllabic filter 20 is shown in the schematic diagram of FIG. 3 together with one prior art circuit serving as coincidence logic 14. Coincidence logic 14 receives an input signal on input terminal 21 from comparator 12 (FIG. 2). This input signal is clocked into four bit shift register 22. When the output signals A0 through A3 provided by shift register 22 are all logical zeros or all logical ones, indicating that the output signal from encoder filter 17 (FIG. 2) has not tracked the input signal Vin and thus that the step size provided by syllabic filter 15 is too small, the output signal from OR gate 29 goes high, thereby connecting capacitor 26 to reference voltage Vref through resistor 25, thereby charging capacitor 26 and increasing the output voltage available on lead 27. This output voltage on lead 27 is applied to encoder filter 17 (FIG. 2), thereby increasing the step size. Conversely, when the step size is too large, the output signal from comparator 12 (FIG. 2) toggles between one and zero and the output signals A0 through A3 provided by shift register 22 are not all logical ones or zeros which cause the output signal from OR gate 29 to go low, thereby discharging capacitor 26 through resistor 25, thereby decreasing the voltage available on output terminal 27. This discrease in output voltage on terminal 27 causes the step size to decrease, providing more accurate conversion of the input signal. However, such a prior art syllabic filter 20 utilizing shift register 22 as coincidence logic has not proven adequate to provide sufficiently low distortion due to poor control of the step size.
In the prior art, syllabic filter 15 has been satisfactorily realized in discrete form by cascading two very low frequency single pole sections, as shown in the schematic diagram of FIG. 4. However, it is highly desirable to fabricate CODECs in integrated circuit form, thereby achieving substantial cost and size reductions over CODECs formed from discrete components. Metal oxide silicon (MOS) technology is especially useful to form very large integrated circuits, typically containing as many as five thousand transistors to form a complex circuit of which a CODEC is only a part. However, in MOS technology, resistor values, capacitor values, and resistor ratios are not highly controllable. The syllabic filter shown on the schematic diagram of FIG. 4 relies on the absolute values of resistors 35 and 37, and 39 and 41, and capacitors 38 and 42 to define the operating characteristics (such as time constants) of the syllabic filter. In order to overcome the problems associated with highly uncontrollable resistor and capacitor absolute values in MOS technology, switched capacitor resistor equivalent technology has been developed, as described in an article by Allstot, et al., entitled "MOS Switched Capacitor Ladder Filters", IEEE Journal of Solid-State Circuits, Volume SC-13, No. 6, December, 1978, pages 806 to 814, which is hereby incorporated by reference. Switched capacitor resistor equivalent technology utilizes a capacitor and appropriate switches to form a resistor equivalent. Because in MOS circuits the thickness of dielectrics are rather constant over the surface of the device, and the size of capacitor plate areas is highly controllable, ratios of capacitances are highly controllable. Thus, the use of switched capacitor resistor equivalent technology allows the highly uncontrollable RC time constants realized by capacitors and resistors to be replaced by highly controllable time constants realized by capacitor ratios.
However, implementation of the syllabic filter of FIG. 4 as an MOS integrated circuit utilizing switched capacitor technology provides very poor performance due to the very long time constants involved. Due to the very long time constants, the capacitance value of the capacitors used to form switched capacitor feedback resistors 37 and 41 become very small causing very small amount of DC feedback, which in turn results in a large DC offset voltage due to clock feedthrough and operational amplifier DC offset voltage. For proper performance the step-size should be controlled very accurately and the DC offset component of the output signal of syllabic filter 15 must be less than one millivolt. DC offset voltages are caused by undesirable feedthrough of clock signals and offset voltages inherent in all operational amplifiers due to finite component mismatches. When implementing the syllabic filter of FIG. 4 using switched capacitor resistor equivalents, an offset voltage of approximately 100 millivolts was realized, thereby precluding use of this type of syllabic filter utilizing switched capacitor technology.